This high degree of integration is especially useful in the manufacture of high-volume products. Items such as cellular and cordless telephones, and wireless LAN equipment benefit from the technology because their product development costs can be spread over hundreds of thousands of units. For instance, Texas Instrument’s TMS320C54x line of DSP ICs have an architecture that has been optimized specifically for use in the baseband sections of wireless terminals and base stations. These low-power (35-100 roW) DSP ICs feature 50 MIPS of processing power. Some also have a hard-wired Viterbi decoding accelerator that reduces a Viterbi “butterfly update” to only four instruction cycles. This addition greatly simplifies channel decoding for applications like GSM handsets and base stations.
Wireless data also is moving into the mainstream, allowing many manufacturers to offer highly integrated solutions. One good example is the SX045 spread-spectrum transceiver, which is offered by American Microsystems Inc., Pocatello, Idaho. Intended for use in wireless LANs which follow the IEEE 802.11 specification, the SX045 contains all the baseband circuitry required for direct sequence spread-spectrum (DSSS) radio. In addition, it performs all radio-control and data-transfer functions of the physical-layer convergence procedure and handles the handshake logic to the physical layer transceiver. A low-cost microcontroller to run the media-access control protocol, a relatively straight-forward modulator/demodulator, and transmitter section are all that’s required for a complete DSSS system.
Above baseband, the move toward integration has been slower, but making substantial advances in the past few years. Achieving integrated RF is not simply a matter of sticking a bunch of fast transistors on a single chip. Some means of matching the impedance between internal elements must still be used. On-chip parasitic effects must be minimized, lest they provide unwanted coupling between different portions of a circuit.
Trench isolation of transistors and careful use of multiple metal layers are only two of the many techniques used to keep crosstalk-induced noise from ruining a chip’s RF performance. Additionally, on-chip passive components are becoming increasingly common on both silicon and GaAs devices. These tiny inductors, capacitors, and resistors are used both for coupling internal devices and for compensating for packaging-induced parasitics on the chip’s inputs and outputs. The same input and output matching networks also are used to raise the RF devices’ impedance to about 50 [ohms], making them less tricky to use.
Integration has done much more than cut the parts count in RF devices. Wireless products using RF ICs often enjoy greatly reduced design times, require much less “tweaking” during unit assembly and testing, and have fewer manufacturing tolerance-induced quality control problems. Both the TQ9143, an integrated 1.4-W, AMPS/TDMA power amplifier from TriQuint Semiconductor, Beaverton, Ore., and the AWT0904, a 35-dBm, GSM/AMPS cellular-band amplifier from Anadigics, Warren, N.J., employ these advanced fabrication techniques. Their on-chip bias and matching networks, and voltage converters significantly reduce the production costs and engineering effort required to produce wireless designs (see Electronic Design, June 24, 1996, p. 87.
Other high-volume applications have led to the development of mixed-signal chips with high levels of digital and analog integration. Functions such as divider networks and control logic can be fabricated on the same chip as voltage-controlled oscillator (VCOs), PLLs, mixers, and even amplifiers. This technique is somewhat easier in the lower-frequency ranges, such as the 49-MHz band used for CB radios, remote-control toys, and cordless telephones.
Motorola Semiconductor, Phoenix, Ariz., is one of the leaders in this area, producing extremely cost-effective chip sets for the very competitive cordless telephone market. One of their latest entries is the MC13110 RF combo IC, a chip that integrates several of the major functions of a cordless telephone into a single IC [ILLUSTRATION FOR FIGURE 1 OMITTED]. Included on the chip are a dual-conversion receiver, a compander, a dual universal PLL, a supply voltage monitor, and a frequency inversion voice scrambler/descrambler security circuit.
Thanks to recent developments, digital technology is no longer limited to baseband applications. Faster analog-to-digital and digital-to-analog converters (ADCs and DACs) are making direct digital synthesis (DDS) of RF signals a possibility for lower-frequency (A-MHz) RF applications. Most converters running above 400 Msamples/s are too bulky and power-hungry for portable applications today, but rapid advances in circuit fabrication will probably see commercially available digital radios passing the GHz threshold before the turn of the century.
These advancements are leading the way for the “software radio,” an all-digital architecture which can be programmed to accommodate any modulation scheme or protocol within its frequency capability. While microphone-to-antenna software radios are not quite a reality today, DSPs are finding their way to the heart of many wireless applications.
While extreme levels of integration can be used for many wireless applications, it is often too costly to implement for all but the commercial products with the highest production volumes.
RF BUILDING BLOCKS
The building-block approach developed by Fujitsu Microelectronics USA, San Jose, Calif., can be used to simplify designs and reduce production costs. Fujitsu has focused on offering its Super Analog component family, a line of smaller, less application-specific integrated “RF building blocks” that can be used in a variety of situations. Currently, their lineup includes the MB5401 integrated low-noise amplifier/mixer, the MB5402 dual low-noise amplifier, and the MB5403 two-stage medium-power amplifier. With a maximum operating frequency of 1.1 GHz, they can simplify both cellular and wireless data applications.
Although current technology does not allow us to apply true functional block-oriented ASIC design techniques to RF circuits yet, Fujitsu does offer a unique “RF Macrocell” technology for speeding up the design process. Known as the Versi-TILE process, it allows designers to work with preengineered bipolar or biCMOS “frames”. The frames contain arrays of transistors, capacitors, and resistors that can be placed on a chip and connected to each other or other frames via two or three metalization layers. There also is a library of predesigned “tiles” which include prescalers, VCOs, buffer amplifiers, and PLLs.
Using the building-block approach, designers can go from supplying a preliminary block diagram to receiving working silicon in eight to twelve weeks. In addition to offering rapid turnaround, Versi-TILE has demonstrated a better than 90% first-pass success rate, based on over 100 designs. If a transition to higher-volume production is desired, the Versi-TILE circuit can be turned into an optimized full-custom design in under six months.
Although these sophisticated chip-level solutions make life much easier, they still can be tricky to use. While component count is sharply reduced, the selection and placement of passives, as well as pc-board layout, are all quite critical. To save designers the task of reinventing the wheel, many RF circuit manufacturers now are offering preengineered reference designs which can be used, at no cost, that can form the heart of a wireless product. In many cases, software for both DSPs and microcontrollers is also supplied. This advantage makes product design a matter of providing packaging, power supply, and custom features that allow for product differentiation.
At its simplest, a reference design includes a components list, schematic, and in the case of an RF device, the all-important pc-board layout artwork. M/A-COM Inc., Lowell, Mass., makes it easy to design its AM52-0001 power amplifier by putting together an evaluation kit containing application notes, a finished 4-layer pc board, all recommended surface-mount passives, RF connectors, and a dc multi-pin connector. Also included in the designers kit is a floppy disk with device performance data and a DXF pc-board layout file [ILLUSTRATION FOR FIGURE 2 OMITTED].
In extremely high-volume markets, chip manufacturers will go to great lengths to make their product easy to use. Analog Devices Inc., Norwood, Mass., has gone so far as to offer a completely certified design for its AD20msp410 GSM cellular telephone chip set. The three-chip solution includes a complete software package that performs all Layer-1 GSM functions. There’s optional software to implement Layers 2 and 3, as well as an application-layer tool kit for developing user interfaces and additional product features. Although it does not sell assembled units itself, Analog Devices went to the trouble of developing a complete cellular telephone design. The design has ETSI type approval, EMI/RFI, and spectral content. Using the preapproved design allows manufacturers bring their products to market in the shortest time possible by eliminating months of compliance testing.
In another case, National Semiconductor, Santa Clara, Calif., is helping electronics manufacturers compete in the highly lucrative market of DECT 1.9-GHz digital cordless telephones by offering a fully developed, type-approved reference design for a full-featured handset and base station. The CompleteDECT solution boasts an advanced RF section with high sensitivity, built-in antenna diversity, ten dialing memories, a 500-m range, a paging function, a 70+ hour standby time, and a 7-hour talk time. Along with a working evaluation unit, the solution includes schematics, parts-lists, pc-board specifications (including Gerber files), shielding specifications, timing diagrams, memory maps, plus test and tuning procedures.
DECT’s simpler cousin, the North American 49-MHz/900-MHz cordless telephone is another market where both cost and time-to-market are critical issues. Recognizing this, Zilog Inc., Campbell, Calif., has developed the ZPhone reference design, a turnkey solution for digital spread-spectrum cordless telephones. Based on its Z87000 and Z87010 baseband chips, and an RF section designed by L.S. Research, Ceadarburg, Wis., the ZPhone design allows manufacturers to produce a product with extended range and high voice quality. The ZPhone is expected to retail for under $140. Both reference designs and complete evaluation kits are available from Zilog.
Harris Semiconductor, Melbourne, Fla., has applied the same formula to its PRISM wireless LAN product line. Recognizing that the IEEE 802.11 wireless LAN standard is a complex, moving target to design products around, Harris has made its 2.4-GHz, 2-Mbit/s, DSSS wireless data system as easy as possible to implement [ILLUSTRATION FOR FIGURE 3 OMITTED]. In addition to a complete reference design, the PRISM chipset’s designers also offer an evaluation kit for prototyping and product development. It consists of two preassembled open-frame PCMCIA transceiver evaluation cards, the PRISM chipset, an industry-standard media-access controller (MAC), RF connectors, PCMCIA extender cards, single-user firmware licenses, diagnostics software, and documentation. If 802.11 compliance is not required, the PRISM system can serve as a platform for the development of customized radios with wider spreading codes and faster data rates which can go as high as 4 Mbits/s.
For one-of-a-kind or low-volume designs, it often pays to completely eliminate all RF engineering by purchasing a complete radio subsystem from another manufacturer, and embedding it in the product. For example, Proxim Inc., Mountain View, Calif., produces the WaveLAN2 product line which allows engineers to integrate a complete wireless LAN subsystem within their products, with a minimum of space, power, or design-time impacts. The unit’s type II PCMCIA card-sized radio data unit is self-contained, requiring only a PCMCIA interface and an antenna connection. RangeLAN cards can be connected conventionally, through an external PCMCIA slot, or embedded within the bowels of its host system. The card’s microminiature coaxial connector, located on its edge, permits an antenna to be attached directly or run to a remote mounting point via a connecting cable. Power consumption (300 mA during transmit) is one of the lowest in the industry, a plus for battery-powered portable applications.
SMARTER DESIGN SOFTWARE
RF design software has existed for nearly as long as computers, but it hasn’t matured at the same rate as its digital cousin. Some of the lag time is due to the lower demand for wireless systems, but the lion’s share belongs to the richer set of problems faced by the RF engineer.
Traditionally, Spice and various flavors of harmonic-balance analysis were used to analyze circuit designs. Spice-type programs can be very accurate for single-frequency operation, but become cumbersome when attempting to model transient behaviors. Additionally, Spice tends to choke on the non-linear noise response in components such as mixers, amplifiers, and downconverters.
Harmonic-balance software also has been used for highly accurate modeling of RF systems. One drawback with the software is that the simulation load grows exponentially with the number of components or frequencies involved. The result is that modeling non-linear components (which produce lots of harmonics), or circuits with much more than 20 devices, can tax even the most powerful workstation.
While these simple tools can be used to design today’s complex RF systems, it resembles constructing a small computer using stone knives and bear skins. Since design and analysis tools have lagged behind, engineers have relied on brassboard prototypes and other trial-and-error techniques. Of course, this meant at least two or three (and often more) passes were needed to get a design sufficiently debugged for production. It can be time consuming and costly enough for board-level designs, but the 12 to 15 months and three to five spins required for moderately complex RF ICs is nearly intolerable for the development of commercial wireless products.
Over the past few years, RF design software has finally begun to mature, and RF design practices have begun to change with it. Modern RF system design practice typically begins with using system-level behavior modeling tools. These tools are used to model a proposed circuit’s general characteristics, and permit engineers to analyze architectural choices. They could include different schemes for segmenting digital and analog functions. They also could look at the effect of various coding and error-correction algorithms upon the circuit’s overall noise and power characteristics.
A LAYERED APPROACH
Once the overall architecture is nailed down, individual portions of the circuit can be designed using software which works at the device level. After a circuit has been captured, it can be run through a new generation of circuit simulators that operate in the frequency domain. This process makes the analysis of a circuit’s response to complex modulation schemes a much less difficult task. Additionally, new advances in EM simulation allow modeling of the physical characteristics of a circuit, such as package-induced parasitics and the complex impedance generated by circuit board or chip-level interconnect traces [ILLUSTRATION FOR FIGURE 4 OMITTED].
This three-level approach offers many advantages. It permits engineers to make better system-level decisions by quickly exploring more design options before committing to a particular architecture. After detailed design begins, accurate circuit simulation helps reduce the amount of costly and time-consuming trial and error required to debug the design once its actually built (see “Past and future: The new world of RF design,” p, 52).
There are several commercially available RF design software packages which can be tailored to suit many different types of products. The Cadence/Alta group, Sunnyvale, Calif., offers a suite of RF design tools that support both system-level and device-level design and simulation. The software from Alta is used primarily for high-level system definition and analysis, while the Cadence package is focused towards detailed, device- and board-level circuit design and analysis.
At the system level, Alta’s EnWave package is a complete solution, created to specifically address the needs of designers working with wireless communications systems. Some of these systems include PCS, wireless LANs, advanced messaging, satellite communications, and digital cellular standards such as IS-95, IS-136, and GSM. Based on Alta’s core simulation technology, the EnWave package includes application-tuned libraries containing hundreds of algorithmic elements that simulate filters, codecs, amplifiers, modulators, mixers, and all the other elements of wireless systems. The package’s RF library allows designers to model distortions and nonlinearities in systems, to permit rapid trade-off analysis.
Alta’s recently introduced Spectre package also adds the capability to perform whole-chip simulations, including non-linear components. This advance is expected to help cut the number of chip-spins required to produce a working product.
Once a first-cut design is complete, it can be transferred for more detailed fine-tuning within the Cadence environment. While files are not directly transferable between the two systems today, work is underway to develop a seamless interface between the macro and micro design packages.
One of the other major players in the field is HP EEsof. They offer a well-integrated array of RF design tools which include simulation software, element libraries, and device modeling systems. Recently, a new suite of RFIC design tools were released with the intent of shortening the design cycle for RF subsystems. It uses multiple simulation technologies combined with highly accurate device models and efficient optimization algorithms. Even the mechanical properties of the semiconductor chips can be modeled to provide analysis of every aspect of a product’s design.
HP EEsof’s basic suite of RF design tools includes a linear simulator, a non-linear simulator, transient and convolution simulators, a statistical design package, a custom element development kit, and a Spice netlist translator able to import Berkley 2G6, PSPICE, and HSPICE netlists. Linkages to HP’s mechanical design packages and electromagnetic simulation software are available to perform accurate chip- or board-level design and analysis.
We can expect that wireless applications will be a rapidly expanding market well into the 21st century, and that the demand for engineers with RF familiarity will continue to be high. Fortunately, today’s design tools and products are making it easier than any time since the discovery of the spark gap transmitter to add wireless capability to your next product. While reference design-based RF subsystems take some of the “fun” out of product development, they give the overworked engineer an opportunity to add value to a product by adding functions and features in more visible locations.